1. Field of the Invention
The present invention relates to a semiconductor storage device including a detecting circuit capable of detecting a shortcircuit between a storage node in a memory cell and a transistor gate, in particular, a high resistance shortcircuit therebetween.
2. Description of the Related Art
In a semiconductor storage device using a DRAM shown in FIG. 12, for example, when a voltage is applied to a gate TG of a transistor 101 in a memory cell 100, the transistor 101 is turned ON and electric charges stored in a capacity 102 are fed to a bit line BL through a storage node SN, accompanied by change of the electric potential of the bit line BL. A sense amplifier (not shown) serves to recognize the electric potential and to output the electric potential as magnitude data.
In the process of manufacturing the memory cell for the semiconductor storage device, a shortcircuit has been caused between the gate TG of the transistor 101 constituting the memory cell 100 or between the gate TG and the storage node SN due to an etching residue or a foreign substance in some cases. The memory cell is not operated well due to the shortcircuit. In order to eliminate this drawback, it has been necessary to detect the shortcircuited memory cell. For example, in the case in which the storage node SN and the gate TG of the transistor 101 are shortcircuited due to a substance having a low resistance, the shortcircuit can easily be detected because the electric potential of the gate TG is transmitted to the storage node SN, resulting in inversion of the electric potential level at the storage node SN.
However, in the case of a high resistance shortcircuit caused by a foreign substance having a high resistance, it has conventionally been difficult to detect the high resistance shortcircuit. In the following description, the "high resistance shortcircuit" implies a shortcircuit caused by a foreign substance having a high resistance which takes a time in transmitting a High-level electric potential at the gate TG of the transistor 101 to the storage node SN to such an extent that the Low-level electric potential at the storage node SN cannot be inverted to the High-level through the High-level electric potential at the gate TG during the operating timing of the conventional sense amplifier.
In the event that the gate TG of the transistor 101 and the storage node SN are shortcircuited with a high resistance due to the contact with the foreign substance, the data reading and sensing operation is completed before the High-level electric potential at the gate TG is transmitted to the storage node SN and inverted during the operation for reading data from the memory cell due to the high resistance shortcircuit during the operation of the conventional sense amplifier when a voltage is applied to the gate TG of the transistor 101 to turn the transistor 101 on and to read the electric potential level at the storage node SN. For this reason, data errors do not occur and the high resistance shortcircuit between the storage node SN and the gate TG cannot therefore be detected.
However, such a high resistance shortcircuit needs to be detected due to the unstable operation of the memory cell. In the conventional art, there have not been methods other than a physical analyzing method such as structural analysis and it has been difficult to detect the high resistance shortcircuit electrically on a circuit bases.
Japanese Patent Laid-Open Publication No. 4-28084 discloses a semiconductor storage device in which the start timing of the operation for detecting a potential difference between a pair of bit lines can be set externally to allow information about a bit line having a small potential difference to be correctly distinguished due to the insufficient capacity of the capacitor of the memory cell and the like so that a device including the bit line can be utilized as a good product. On the other hand, the present invention has an object to detect a high resistance shortcircuit between the gate of the transistor in the memory cell and the storage node, in which the operation timing of the sense amplifier in a test mode or the like is delayed for a predetermined period such that the high resistance shortcircuit can be detected. Thus, the present invention is different from the Japanese Patent Laid-Open Publication No. 4-28084.
Japanese Patent Laid-Open Publication No. 7-85668 discloses a semiconductor storage device which is intended for reducing noises during the operation of a sense amplifier by providing a capacity between an activating control circuit and the sense amplifier to prevent a rapid change in the power source of the sense amplifier. Similarly, Japanese Patent Laid-Open Publication No. 5-144263 discloses a semiconductor storage device in which a plurality of delay circuits constituted by using a resistance and a capacity are provided in a sub-block unit dividing a bit line, the operation timing of the sense amplifiers between banks is shifted and the number of the sense amplifiers operating is simultaneously decreased by utilizing the fact that a time is varied for transmitting a change in the electric potential of the bit line caused by the electric potential of the cell to the sense amplifier according to a distance between word lines selected by the sense amplifier during multi-bank operation so that an instantaneous operating current and noises made during the operation can be reduced, respectively.
Moreover, Japanese Patent Laid-Open Publication No. 62-202398 discloses a semiconductor storage device in which a circuit for detecting that a word line is boosted to have the threshold of a transfer gate of a cell and a sense amplifier is operated in a timing in which the word line is boosted reliably to minimize the delay of a boost time for the word line, thereby increasing a speed.